1. Field of the Invention
The present invention relates to an input circuit for a semiconductor memory device and, more particularly, to an input circuit for a semiconductor memory device for generating an internal signal in accordance with an external signal changing from a first logical potential to a second logical potential at a certain time point, and for applying the internal signal to an internal circuitry.
2. Description of the Background Art
Conventionally, at various control signal input terminals of a dynamic random access memory (hereinafter referred to as a DRAM), an input buffer for converting an externally applied control signal /EXT to an internal control signal /INT and for applying it to an internal circuitry has been provided.
FIG. 8 is a schematic diagram showing the structure of a conventional input buffer 80 for a DRAM.
Referring to FIG. 8, input buffer 80 includes an NOR gate 81, an inverter 82 and a P channel MOS transistor 83. One input node 81a of NOR gate 81 receives an external signal /EXT, and the other input 81b is connected to a line 71 at the ground potential GND (hereinafter referred to as the ground line).
NOR gate 81 includes, as shown in FIG. 9, P channel MOS transistors 91 and 92 connected in series between power supply line 70 and output node N81, and N channel MOS transistors 93 and 94 connected in parallel between output node N81 and ground line 71. MOS transistors 92 and 93 have their gates connected to one input node 81a, and MOS transistors 91 and 94 have their gates connected to the other input node 81b. Since the other input node 81b of NOR gate 81 is grounded, NOR gate 81 operates as an inverter consisting of MOS transistors 92 and 93 with respect to external signal /EXT.
Inverter 82 receives an output from NOR gate 81 and outputs an internal signal /INT. P channel MOS transistor 83 is connected between a line of a power supply potential Vcc (hereinafter referred to as the power supply line) 70 and an input node of an inverter 82, and receives at its gate an output from inverter 82. Inverter 82 and P channel MOS transistor 83 constitute a half latch circuit.
When the external signal /EXT falls from an inactive "H" level to an active "L" level, the output from inverter 82, that is, internal signal /INT falls from the "H" level to the "L" level, P channel MOS transistor 83 is rendered conductive and internal signal /INT is latched at the "L" level. When external signal /EXT rises from the active level of "L" to the inactive level of "H", internal signal /INT rises from "L" level to "H" level, P channel MOS transistor 83 is rendered non-conductive, and the half latch is canceled.
Since the conventional input buffer 80 is structured as described above, when data output from DRAM is started and power supply potential Vcc lowers temporarily while the external signal /EXT is at the active level of "L", the potential at output node N81 of NOR gate 81 lowers, and the output from inverter 82, that is, the level of internal signal /INT rises slightly. This may result in a malfunction of an internal circuitry which is controlled by the internal signal /INT.